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cpuid.go 27 KB

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  1. // Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
  2. // Package cpuid provides information about the CPU running the current program.
  3. //
  4. // CPU features are detected on startup, and kept for fast access through the life of the application.
  5. // Currently x86 / x64 (AMD64) is supported.
  6. //
  7. // You can access the CPU information by accessing the shared CPU variable of the cpuid library.
  8. //
  9. // Package home: https://github.com/klauspost/cpuid
  10. package cpuid
  11. import "strings"
  12. // Vendor is a representation of a CPU vendor.
  13. type Vendor int
  14. const (
  15. Other Vendor = iota
  16. Intel
  17. AMD
  18. VIA
  19. Transmeta
  20. NSC
  21. KVM // Kernel-based Virtual Machine
  22. MSVM // Microsoft Hyper-V or Windows Virtual PC
  23. VMware
  24. XenHVM
  25. )
  26. const (
  27. CMOV = 1 << iota // i686 CMOV
  28. NX // NX (No-Execute) bit
  29. AMD3DNOW // AMD 3DNOW
  30. AMD3DNOWEXT // AMD 3DNowExt
  31. MMX // standard MMX
  32. MMXEXT // SSE integer functions or AMD MMX ext
  33. SSE // SSE functions
  34. SSE2 // P4 SSE functions
  35. SSE3 // Prescott SSE3 functions
  36. SSSE3 // Conroe SSSE3 functions
  37. SSE4 // Penryn SSE4.1 functions
  38. SSE4A // AMD Barcelona microarchitecture SSE4a instructions
  39. SSE42 // Nehalem SSE4.2 functions
  40. AVX // AVX functions
  41. AVX2 // AVX2 functions
  42. FMA3 // Intel FMA 3
  43. FMA4 // Bulldozer FMA4 functions
  44. XOP // Bulldozer XOP functions
  45. F16C // Half-precision floating-point conversion
  46. BMI1 // Bit Manipulation Instruction Set 1
  47. BMI2 // Bit Manipulation Instruction Set 2
  48. TBM // AMD Trailing Bit Manipulation
  49. LZCNT // LZCNT instruction
  50. POPCNT // POPCNT instruction
  51. AESNI // Advanced Encryption Standard New Instructions
  52. CLMUL // Carry-less Multiplication
  53. HTT // Hyperthreading (enabled)
  54. HLE // Hardware Lock Elision
  55. RTM // Restricted Transactional Memory
  56. RDRAND // RDRAND instruction is available
  57. RDSEED // RDSEED instruction is available
  58. ADX // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
  59. SHA // Intel SHA Extensions
  60. AVX512F // AVX-512 Foundation
  61. AVX512DQ // AVX-512 Doubleword and Quadword Instructions
  62. AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
  63. AVX512PF // AVX-512 Prefetch Instructions
  64. AVX512ER // AVX-512 Exponential and Reciprocal Instructions
  65. AVX512CD // AVX-512 Conflict Detection Instructions
  66. AVX512BW // AVX-512 Byte and Word Instructions
  67. AVX512VL // AVX-512 Vector Length Extensions
  68. AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
  69. MPX // Intel MPX (Memory Protection Extensions)
  70. ERMS // Enhanced REP MOVSB/STOSB
  71. RDTSCP // RDTSCP Instruction
  72. CX16 // CMPXCHG16B Instruction
  73. SGX // Software Guard Extensions
  74. // Performance indicators
  75. SSE2SLOW // SSE2 is supported, but usually not faster
  76. SSE3SLOW // SSE3 is supported, but usually not faster
  77. ATOM // Atom processor, some SSSE3 instructions are slower
  78. )
  79. var flagNames = map[Flags]string{
  80. CMOV: "CMOV", // i686 CMOV
  81. NX: "NX", // NX (No-Execute) bit
  82. AMD3DNOW: "AMD3DNOW", // AMD 3DNOW
  83. AMD3DNOWEXT: "AMD3DNOWEXT", // AMD 3DNowExt
  84. MMX: "MMX", // Standard MMX
  85. MMXEXT: "MMXEXT", // SSE integer functions or AMD MMX ext
  86. SSE: "SSE", // SSE functions
  87. SSE2: "SSE2", // P4 SSE2 functions
  88. SSE3: "SSE3", // Prescott SSE3 functions
  89. SSSE3: "SSSE3", // Conroe SSSE3 functions
  90. SSE4: "SSE4.1", // Penryn SSE4.1 functions
  91. SSE4A: "SSE4A", // AMD Barcelona microarchitecture SSE4a instructions
  92. SSE42: "SSE4.2", // Nehalem SSE4.2 functions
  93. AVX: "AVX", // AVX functions
  94. AVX2: "AVX2", // AVX functions
  95. FMA3: "FMA3", // Intel FMA 3
  96. FMA4: "FMA4", // Bulldozer FMA4 functions
  97. XOP: "XOP", // Bulldozer XOP functions
  98. F16C: "F16C", // Half-precision floating-point conversion
  99. BMI1: "BMI1", // Bit Manipulation Instruction Set 1
  100. BMI2: "BMI2", // Bit Manipulation Instruction Set 2
  101. TBM: "TBM", // AMD Trailing Bit Manipulation
  102. LZCNT: "LZCNT", // LZCNT instruction
  103. POPCNT: "POPCNT", // POPCNT instruction
  104. AESNI: "AESNI", // Advanced Encryption Standard New Instructions
  105. CLMUL: "CLMUL", // Carry-less Multiplication
  106. HTT: "HTT", // Hyperthreading (enabled)
  107. HLE: "HLE", // Hardware Lock Elision
  108. RTM: "RTM", // Restricted Transactional Memory
  109. RDRAND: "RDRAND", // RDRAND instruction is available
  110. RDSEED: "RDSEED", // RDSEED instruction is available
  111. ADX: "ADX", // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
  112. SHA: "SHA", // Intel SHA Extensions
  113. AVX512F: "AVX512F", // AVX-512 Foundation
  114. AVX512DQ: "AVX512DQ", // AVX-512 Doubleword and Quadword Instructions
  115. AVX512IFMA: "AVX512IFMA", // AVX-512 Integer Fused Multiply-Add Instructions
  116. AVX512PF: "AVX512PF", // AVX-512 Prefetch Instructions
  117. AVX512ER: "AVX512ER", // AVX-512 Exponential and Reciprocal Instructions
  118. AVX512CD: "AVX512CD", // AVX-512 Conflict Detection Instructions
  119. AVX512BW: "AVX512BW", // AVX-512 Byte and Word Instructions
  120. AVX512VL: "AVX512VL", // AVX-512 Vector Length Extensions
  121. AVX512VBMI: "AVX512VBMI", // AVX-512 Vector Bit Manipulation Instructions
  122. MPX: "MPX", // Intel MPX (Memory Protection Extensions)
  123. ERMS: "ERMS", // Enhanced REP MOVSB/STOSB
  124. RDTSCP: "RDTSCP", // RDTSCP Instruction
  125. CX16: "CX16", // CMPXCHG16B Instruction
  126. SGX: "SGX", // Software Guard Extensions
  127. // Performance indicators
  128. SSE2SLOW: "SSE2SLOW", // SSE2 supported, but usually not faster
  129. SSE3SLOW: "SSE3SLOW", // SSE3 supported, but usually not faster
  130. ATOM: "ATOM", // Atom processor, some SSSE3 instructions are slower
  131. }
  132. // CPUInfo contains information about the detected system CPU.
  133. type CPUInfo struct {
  134. BrandName string // Brand name reported by the CPU
  135. VendorID Vendor // Comparable CPU vendor ID
  136. Features Flags // Features of the CPU
  137. PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable.
  138. ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable.
  139. LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
  140. Family int // CPU family number
  141. Model int // CPU model number
  142. CacheLine int // Cache line size in bytes. Will be 0 if undetectable.
  143. Cache struct {
  144. L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
  145. L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected
  146. L2 int // L2 Cache (per core or shared). Will be -1 if undetected
  147. L3 int // L3 Instruction Cache (per core or shared). Will be -1 if undetected
  148. }
  149. SGX SGXSupport
  150. maxFunc uint32
  151. maxExFunc uint32
  152. }
  153. var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
  154. var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32)
  155. var xgetbv func(index uint32) (eax, edx uint32)
  156. var rdtscpAsm func() (eax, ebx, ecx, edx uint32)
  157. // CPU contains information about the CPU as detected on startup,
  158. // or when Detect last was called.
  159. //
  160. // Use this as the primary entry point to you data,
  161. // this way queries are
  162. var CPU CPUInfo
  163. func init() {
  164. initCPU()
  165. Detect()
  166. }
  167. // Detect will re-detect current CPU info.
  168. // This will replace the content of the exported CPU variable.
  169. //
  170. // Unless you expect the CPU to change while you are running your program
  171. // you should not need to call this function.
  172. // If you call this, you must ensure that no other goroutine is accessing the
  173. // exported CPU variable.
  174. func Detect() {
  175. CPU.maxFunc = maxFunctionID()
  176. CPU.maxExFunc = maxExtendedFunction()
  177. CPU.BrandName = brandName()
  178. CPU.CacheLine = cacheLine()
  179. CPU.Family, CPU.Model = familyModel()
  180. CPU.Features = support()
  181. CPU.SGX = sgx(CPU.Features&SGX != 0)
  182. CPU.ThreadsPerCore = threadsPerCore()
  183. CPU.LogicalCores = logicalCores()
  184. CPU.PhysicalCores = physicalCores()
  185. CPU.VendorID = vendorID()
  186. CPU.cacheSize()
  187. }
  188. // Generated here: http://play.golang.org/p/BxFH2Gdc0G
  189. // Cmov indicates support of CMOV instructions
  190. func (c CPUInfo) Cmov() bool {
  191. return c.Features&CMOV != 0
  192. }
  193. // Amd3dnow indicates support of AMD 3DNOW! instructions
  194. func (c CPUInfo) Amd3dnow() bool {
  195. return c.Features&AMD3DNOW != 0
  196. }
  197. // Amd3dnowExt indicates support of AMD 3DNOW! Extended instructions
  198. func (c CPUInfo) Amd3dnowExt() bool {
  199. return c.Features&AMD3DNOWEXT != 0
  200. }
  201. // MMX indicates support of MMX instructions
  202. func (c CPUInfo) MMX() bool {
  203. return c.Features&MMX != 0
  204. }
  205. // MMXExt indicates support of MMXEXT instructions
  206. // (SSE integer functions or AMD MMX ext)
  207. func (c CPUInfo) MMXExt() bool {
  208. return c.Features&MMXEXT != 0
  209. }
  210. // SSE indicates support of SSE instructions
  211. func (c CPUInfo) SSE() bool {
  212. return c.Features&SSE != 0
  213. }
  214. // SSE2 indicates support of SSE 2 instructions
  215. func (c CPUInfo) SSE2() bool {
  216. return c.Features&SSE2 != 0
  217. }
  218. // SSE3 indicates support of SSE 3 instructions
  219. func (c CPUInfo) SSE3() bool {
  220. return c.Features&SSE3 != 0
  221. }
  222. // SSSE3 indicates support of SSSE 3 instructions
  223. func (c CPUInfo) SSSE3() bool {
  224. return c.Features&SSSE3 != 0
  225. }
  226. // SSE4 indicates support of SSE 4 (also called SSE 4.1) instructions
  227. func (c CPUInfo) SSE4() bool {
  228. return c.Features&SSE4 != 0
  229. }
  230. // SSE42 indicates support of SSE4.2 instructions
  231. func (c CPUInfo) SSE42() bool {
  232. return c.Features&SSE42 != 0
  233. }
  234. // AVX indicates support of AVX instructions
  235. // and operating system support of AVX instructions
  236. func (c CPUInfo) AVX() bool {
  237. return c.Features&AVX != 0
  238. }
  239. // AVX2 indicates support of AVX2 instructions
  240. func (c CPUInfo) AVX2() bool {
  241. return c.Features&AVX2 != 0
  242. }
  243. // FMA3 indicates support of FMA3 instructions
  244. func (c CPUInfo) FMA3() bool {
  245. return c.Features&FMA3 != 0
  246. }
  247. // FMA4 indicates support of FMA4 instructions
  248. func (c CPUInfo) FMA4() bool {
  249. return c.Features&FMA4 != 0
  250. }
  251. // XOP indicates support of XOP instructions
  252. func (c CPUInfo) XOP() bool {
  253. return c.Features&XOP != 0
  254. }
  255. // F16C indicates support of F16C instructions
  256. func (c CPUInfo) F16C() bool {
  257. return c.Features&F16C != 0
  258. }
  259. // BMI1 indicates support of BMI1 instructions
  260. func (c CPUInfo) BMI1() bool {
  261. return c.Features&BMI1 != 0
  262. }
  263. // BMI2 indicates support of BMI2 instructions
  264. func (c CPUInfo) BMI2() bool {
  265. return c.Features&BMI2 != 0
  266. }
  267. // TBM indicates support of TBM instructions
  268. // (AMD Trailing Bit Manipulation)
  269. func (c CPUInfo) TBM() bool {
  270. return c.Features&TBM != 0
  271. }
  272. // Lzcnt indicates support of LZCNT instruction
  273. func (c CPUInfo) Lzcnt() bool {
  274. return c.Features&LZCNT != 0
  275. }
  276. // Popcnt indicates support of POPCNT instruction
  277. func (c CPUInfo) Popcnt() bool {
  278. return c.Features&POPCNT != 0
  279. }
  280. // HTT indicates the processor has Hyperthreading enabled
  281. func (c CPUInfo) HTT() bool {
  282. return c.Features&HTT != 0
  283. }
  284. // SSE2Slow indicates that SSE2 may be slow on this processor
  285. func (c CPUInfo) SSE2Slow() bool {
  286. return c.Features&SSE2SLOW != 0
  287. }
  288. // SSE3Slow indicates that SSE3 may be slow on this processor
  289. func (c CPUInfo) SSE3Slow() bool {
  290. return c.Features&SSE3SLOW != 0
  291. }
  292. // AesNi indicates support of AES-NI instructions
  293. // (Advanced Encryption Standard New Instructions)
  294. func (c CPUInfo) AesNi() bool {
  295. return c.Features&AESNI != 0
  296. }
  297. // Clmul indicates support of CLMUL instructions
  298. // (Carry-less Multiplication)
  299. func (c CPUInfo) Clmul() bool {
  300. return c.Features&CLMUL != 0
  301. }
  302. // NX indicates support of NX (No-Execute) bit
  303. func (c CPUInfo) NX() bool {
  304. return c.Features&NX != 0
  305. }
  306. // SSE4A indicates support of AMD Barcelona microarchitecture SSE4a instructions
  307. func (c CPUInfo) SSE4A() bool {
  308. return c.Features&SSE4A != 0
  309. }
  310. // HLE indicates support of Hardware Lock Elision
  311. func (c CPUInfo) HLE() bool {
  312. return c.Features&HLE != 0
  313. }
  314. // RTM indicates support of Restricted Transactional Memory
  315. func (c CPUInfo) RTM() bool {
  316. return c.Features&RTM != 0
  317. }
  318. // Rdrand indicates support of RDRAND instruction is available
  319. func (c CPUInfo) Rdrand() bool {
  320. return c.Features&RDRAND != 0
  321. }
  322. // Rdseed indicates support of RDSEED instruction is available
  323. func (c CPUInfo) Rdseed() bool {
  324. return c.Features&RDSEED != 0
  325. }
  326. // ADX indicates support of Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
  327. func (c CPUInfo) ADX() bool {
  328. return c.Features&ADX != 0
  329. }
  330. // SHA indicates support of Intel SHA Extensions
  331. func (c CPUInfo) SHA() bool {
  332. return c.Features&SHA != 0
  333. }
  334. // AVX512F indicates support of AVX-512 Foundation
  335. func (c CPUInfo) AVX512F() bool {
  336. return c.Features&AVX512F != 0
  337. }
  338. // AVX512DQ indicates support of AVX-512 Doubleword and Quadword Instructions
  339. func (c CPUInfo) AVX512DQ() bool {
  340. return c.Features&AVX512DQ != 0
  341. }
  342. // AVX512IFMA indicates support of AVX-512 Integer Fused Multiply-Add Instructions
  343. func (c CPUInfo) AVX512IFMA() bool {
  344. return c.Features&AVX512IFMA != 0
  345. }
  346. // AVX512PF indicates support of AVX-512 Prefetch Instructions
  347. func (c CPUInfo) AVX512PF() bool {
  348. return c.Features&AVX512PF != 0
  349. }
  350. // AVX512ER indicates support of AVX-512 Exponential and Reciprocal Instructions
  351. func (c CPUInfo) AVX512ER() bool {
  352. return c.Features&AVX512ER != 0
  353. }
  354. // AVX512CD indicates support of AVX-512 Conflict Detection Instructions
  355. func (c CPUInfo) AVX512CD() bool {
  356. return c.Features&AVX512CD != 0
  357. }
  358. // AVX512BW indicates support of AVX-512 Byte and Word Instructions
  359. func (c CPUInfo) AVX512BW() bool {
  360. return c.Features&AVX512BW != 0
  361. }
  362. // AVX512VL indicates support of AVX-512 Vector Length Extensions
  363. func (c CPUInfo) AVX512VL() bool {
  364. return c.Features&AVX512VL != 0
  365. }
  366. // AVX512VBMI indicates support of AVX-512 Vector Bit Manipulation Instructions
  367. func (c CPUInfo) AVX512VBMI() bool {
  368. return c.Features&AVX512VBMI != 0
  369. }
  370. // MPX indicates support of Intel MPX (Memory Protection Extensions)
  371. func (c CPUInfo) MPX() bool {
  372. return c.Features&MPX != 0
  373. }
  374. // ERMS indicates support of Enhanced REP MOVSB/STOSB
  375. func (c CPUInfo) ERMS() bool {
  376. return c.Features&ERMS != 0
  377. }
  378. func (c CPUInfo) RDTSCP() bool {
  379. return c.Features&RDTSCP != 0
  380. }
  381. func (c CPUInfo) CX16() bool {
  382. return c.Features&CX16 != 0
  383. }
  384. // Atom indicates an Atom processor
  385. func (c CPUInfo) Atom() bool {
  386. return c.Features&ATOM != 0
  387. }
  388. // Intel returns true if vendor is recognized as Intel
  389. func (c CPUInfo) Intel() bool {
  390. return c.VendorID == Intel
  391. }
  392. // AMD returns true if vendor is recognized as AMD
  393. func (c CPUInfo) AMD() bool {
  394. return c.VendorID == AMD
  395. }
  396. // Transmeta returns true if vendor is recognized as Transmeta
  397. func (c CPUInfo) Transmeta() bool {
  398. return c.VendorID == Transmeta
  399. }
  400. // NSC returns true if vendor is recognized as National Semiconductor
  401. func (c CPUInfo) NSC() bool {
  402. return c.VendorID == NSC
  403. }
  404. // VIA returns true if vendor is recognized as VIA
  405. func (c CPUInfo) VIA() bool {
  406. return c.VendorID == VIA
  407. }
  408. // RTCounter returns the 64-bit time-stamp counter
  409. // Uses the RDTSCP instruction. The value 0 is returned
  410. // if the CPU does not support the instruction.
  411. func (c CPUInfo) RTCounter() uint64 {
  412. if !c.RDTSCP() {
  413. return 0
  414. }
  415. a, _, _, d := rdtscpAsm()
  416. return uint64(a) | (uint64(d) << 32)
  417. }
  418. // Ia32TscAux returns the IA32_TSC_AUX part of the RDTSCP.
  419. // This variable is OS dependent, but on Linux contains information
  420. // about the current cpu/core the code is running on.
  421. // If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned.
  422. func (c CPUInfo) Ia32TscAux() uint32 {
  423. if !c.RDTSCP() {
  424. return 0
  425. }
  426. _, _, ecx, _ := rdtscpAsm()
  427. return ecx
  428. }
  429. // LogicalCPU will return the Logical CPU the code is currently executing on.
  430. // This is likely to change when the OS re-schedules the running thread
  431. // to another CPU.
  432. // If the current core cannot be detected, -1 will be returned.
  433. func (c CPUInfo) LogicalCPU() int {
  434. if c.maxFunc < 1 {
  435. return -1
  436. }
  437. _, ebx, _, _ := cpuid(1)
  438. return int(ebx >> 24)
  439. }
  440. // VM Will return true if the cpu id indicates we are in
  441. // a virtual machine. This is only a hint, and will very likely
  442. // have many false negatives.
  443. func (c CPUInfo) VM() bool {
  444. switch c.VendorID {
  445. case MSVM, KVM, VMware, XenHVM:
  446. return true
  447. }
  448. return false
  449. }
  450. // Flags contains detected cpu features and caracteristics
  451. type Flags uint64
  452. // String returns a string representation of the detected
  453. // CPU features.
  454. func (f Flags) String() string {
  455. return strings.Join(f.Strings(), ",")
  456. }
  457. // Strings returns and array of the detected features.
  458. func (f Flags) Strings() []string {
  459. s := support()
  460. r := make([]string, 0, 20)
  461. for i := uint(0); i < 64; i++ {
  462. key := Flags(1 << i)
  463. val := flagNames[key]
  464. if s&key != 0 {
  465. r = append(r, val)
  466. }
  467. }
  468. return r
  469. }
  470. func maxExtendedFunction() uint32 {
  471. eax, _, _, _ := cpuid(0x80000000)
  472. return eax
  473. }
  474. func maxFunctionID() uint32 {
  475. a, _, _, _ := cpuid(0)
  476. return a
  477. }
  478. func brandName() string {
  479. if maxExtendedFunction() >= 0x80000004 {
  480. v := make([]uint32, 0, 48)
  481. for i := uint32(0); i < 3; i++ {
  482. a, b, c, d := cpuid(0x80000002 + i)
  483. v = append(v, a, b, c, d)
  484. }
  485. return strings.Trim(string(valAsString(v...)), " ")
  486. }
  487. return "unknown"
  488. }
  489. func threadsPerCore() int {
  490. mfi := maxFunctionID()
  491. if mfi < 0x4 || vendorID() != Intel {
  492. return 1
  493. }
  494. if mfi < 0xb {
  495. _, b, _, d := cpuid(1)
  496. if (d & (1 << 28)) != 0 {
  497. // v will contain logical core count
  498. v := (b >> 16) & 255
  499. if v > 1 {
  500. a4, _, _, _ := cpuid(4)
  501. // physical cores
  502. v2 := (a4 >> 26) + 1
  503. if v2 > 0 {
  504. return int(v) / int(v2)
  505. }
  506. }
  507. }
  508. return 1
  509. }
  510. _, b, _, _ := cpuidex(0xb, 0)
  511. if b&0xffff == 0 {
  512. return 1
  513. }
  514. return int(b & 0xffff)
  515. }
  516. func logicalCores() int {
  517. mfi := maxFunctionID()
  518. switch vendorID() {
  519. case Intel:
  520. // Use this on old Intel processors
  521. if mfi < 0xb {
  522. if mfi < 1 {
  523. return 0
  524. }
  525. // CPUID.1:EBX[23:16] represents the maximum number of addressable IDs (initial APIC ID)
  526. // that can be assigned to logical processors in a physical package.
  527. // The value may not be the same as the number of logical processors that are present in the hardware of a physical package.
  528. _, ebx, _, _ := cpuid(1)
  529. logical := (ebx >> 16) & 0xff
  530. return int(logical)
  531. }
  532. _, b, _, _ := cpuidex(0xb, 1)
  533. return int(b & 0xffff)
  534. case AMD:
  535. _, b, _, _ := cpuid(1)
  536. return int((b >> 16) & 0xff)
  537. default:
  538. return 0
  539. }
  540. }
  541. func familyModel() (int, int) {
  542. if maxFunctionID() < 0x1 {
  543. return 0, 0
  544. }
  545. eax, _, _, _ := cpuid(1)
  546. family := ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff)
  547. model := ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0)
  548. return int(family), int(model)
  549. }
  550. func physicalCores() int {
  551. switch vendorID() {
  552. case Intel:
  553. return logicalCores() / threadsPerCore()
  554. case AMD:
  555. if maxExtendedFunction() >= 0x80000008 {
  556. _, _, c, _ := cpuid(0x80000008)
  557. return int(c&0xff) + 1
  558. }
  559. }
  560. return 0
  561. }
  562. // Except from http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID
  563. var vendorMapping = map[string]Vendor{
  564. "AMDisbetter!": AMD,
  565. "AuthenticAMD": AMD,
  566. "CentaurHauls": VIA,
  567. "GenuineIntel": Intel,
  568. "TransmetaCPU": Transmeta,
  569. "GenuineTMx86": Transmeta,
  570. "Geode by NSC": NSC,
  571. "VIA VIA VIA ": VIA,
  572. "KVMKVMKVMKVM": KVM,
  573. "Microsoft Hv": MSVM,
  574. "VMwareVMware": VMware,
  575. "XenVMMXenVMM": XenHVM,
  576. }
  577. func vendorID() Vendor {
  578. _, b, c, d := cpuid(0)
  579. v := valAsString(b, d, c)
  580. vend, ok := vendorMapping[string(v)]
  581. if !ok {
  582. return Other
  583. }
  584. return vend
  585. }
  586. func cacheLine() int {
  587. if maxFunctionID() < 0x1 {
  588. return 0
  589. }
  590. _, ebx, _, _ := cpuid(1)
  591. cache := (ebx & 0xff00) >> 5 // cflush size
  592. if cache == 0 && maxExtendedFunction() >= 0x80000006 {
  593. _, _, ecx, _ := cpuid(0x80000006)
  594. cache = ecx & 0xff // cacheline size
  595. }
  596. // TODO: Read from Cache and TLB Information
  597. return int(cache)
  598. }
  599. func (c *CPUInfo) cacheSize() {
  600. c.Cache.L1D = -1
  601. c.Cache.L1I = -1
  602. c.Cache.L2 = -1
  603. c.Cache.L3 = -1
  604. vendor := vendorID()
  605. switch vendor {
  606. case Intel:
  607. if maxFunctionID() < 4 {
  608. return
  609. }
  610. for i := uint32(0); ; i++ {
  611. eax, ebx, ecx, _ := cpuidex(4, i)
  612. cacheType := eax & 15
  613. if cacheType == 0 {
  614. break
  615. }
  616. cacheLevel := (eax >> 5) & 7
  617. coherency := int(ebx&0xfff) + 1
  618. partitions := int((ebx>>12)&0x3ff) + 1
  619. associativity := int((ebx>>22)&0x3ff) + 1
  620. sets := int(ecx) + 1
  621. size := associativity * partitions * coherency * sets
  622. switch cacheLevel {
  623. case 1:
  624. if cacheType == 1 {
  625. // 1 = Data Cache
  626. c.Cache.L1D = size
  627. } else if cacheType == 2 {
  628. // 2 = Instruction Cache
  629. c.Cache.L1I = size
  630. } else {
  631. if c.Cache.L1D < 0 {
  632. c.Cache.L1I = size
  633. }
  634. if c.Cache.L1I < 0 {
  635. c.Cache.L1I = size
  636. }
  637. }
  638. case 2:
  639. c.Cache.L2 = size
  640. case 3:
  641. c.Cache.L3 = size
  642. }
  643. }
  644. case AMD:
  645. // Untested.
  646. if maxExtendedFunction() < 0x80000005 {
  647. return
  648. }
  649. _, _, ecx, edx := cpuid(0x80000005)
  650. c.Cache.L1D = int(((ecx >> 24) & 0xFF) * 1024)
  651. c.Cache.L1I = int(((edx >> 24) & 0xFF) * 1024)
  652. if maxExtendedFunction() < 0x80000006 {
  653. return
  654. }
  655. _, _, ecx, _ = cpuid(0x80000006)
  656. c.Cache.L2 = int(((ecx >> 16) & 0xFFFF) * 1024)
  657. }
  658. return
  659. }
  660. type SGXSupport struct {
  661. Available bool
  662. SGX1Supported bool
  663. SGX2Supported bool
  664. MaxEnclaveSizeNot64 int64
  665. MaxEnclaveSize64 int64
  666. }
  667. func sgx(available bool) (rval SGXSupport) {
  668. rval.Available = available
  669. if !available {
  670. return
  671. }
  672. a, _, _, d := cpuidex(0x12, 0)
  673. rval.SGX1Supported = a&0x01 != 0
  674. rval.SGX2Supported = a&0x02 != 0
  675. rval.MaxEnclaveSizeNot64 = 1 << (d & 0xFF) // pow 2
  676. rval.MaxEnclaveSize64 = 1 << ((d >> 8) & 0xFF) // pow 2
  677. return
  678. }
  679. func support() Flags {
  680. mfi := maxFunctionID()
  681. vend := vendorID()
  682. if mfi < 0x1 {
  683. return 0
  684. }
  685. rval := uint64(0)
  686. _, _, c, d := cpuid(1)
  687. if (d & (1 << 15)) != 0 {
  688. rval |= CMOV
  689. }
  690. if (d & (1 << 23)) != 0 {
  691. rval |= MMX
  692. }
  693. if (d & (1 << 25)) != 0 {
  694. rval |= MMXEXT
  695. }
  696. if (d & (1 << 25)) != 0 {
  697. rval |= SSE
  698. }
  699. if (d & (1 << 26)) != 0 {
  700. rval |= SSE2
  701. }
  702. if (c & 1) != 0 {
  703. rval |= SSE3
  704. }
  705. if (c & 0x00000200) != 0 {
  706. rval |= SSSE3
  707. }
  708. if (c & 0x00080000) != 0 {
  709. rval |= SSE4
  710. }
  711. if (c & 0x00100000) != 0 {
  712. rval |= SSE42
  713. }
  714. if (c & (1 << 25)) != 0 {
  715. rval |= AESNI
  716. }
  717. if (c & (1 << 1)) != 0 {
  718. rval |= CLMUL
  719. }
  720. if c&(1<<23) != 0 {
  721. rval |= POPCNT
  722. }
  723. if c&(1<<30) != 0 {
  724. rval |= RDRAND
  725. }
  726. if c&(1<<29) != 0 {
  727. rval |= F16C
  728. }
  729. if c&(1<<13) != 0 {
  730. rval |= CX16
  731. }
  732. if vend == Intel && (d&(1<<28)) != 0 && mfi >= 4 {
  733. if threadsPerCore() > 1 {
  734. rval |= HTT
  735. }
  736. }
  737. // Check XGETBV, OXSAVE and AVX bits
  738. if c&(1<<26) != 0 && c&(1<<27) != 0 && c&(1<<28) != 0 {
  739. // Check for OS support
  740. eax, _ := xgetbv(0)
  741. if (eax & 0x6) == 0x6 {
  742. rval |= AVX
  743. if (c & 0x00001000) != 0 {
  744. rval |= FMA3
  745. }
  746. }
  747. }
  748. // Check AVX2, AVX2 requires OS support, but BMI1/2 don't.
  749. if mfi >= 7 {
  750. _, ebx, ecx, _ := cpuidex(7, 0)
  751. if (rval&AVX) != 0 && (ebx&0x00000020) != 0 {
  752. rval |= AVX2
  753. }
  754. if (ebx & 0x00000008) != 0 {
  755. rval |= BMI1
  756. if (ebx & 0x00000100) != 0 {
  757. rval |= BMI2
  758. }
  759. }
  760. if ebx&(1<<2) != 0 {
  761. rval |= SGX
  762. }
  763. if ebx&(1<<4) != 0 {
  764. rval |= HLE
  765. }
  766. if ebx&(1<<9) != 0 {
  767. rval |= ERMS
  768. }
  769. if ebx&(1<<11) != 0 {
  770. rval |= RTM
  771. }
  772. if ebx&(1<<14) != 0 {
  773. rval |= MPX
  774. }
  775. if ebx&(1<<18) != 0 {
  776. rval |= RDSEED
  777. }
  778. if ebx&(1<<19) != 0 {
  779. rval |= ADX
  780. }
  781. if ebx&(1<<29) != 0 {
  782. rval |= SHA
  783. }
  784. // Only detect AVX-512 features if XGETBV is supported
  785. if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
  786. // Check for OS support
  787. eax, _ := xgetbv(0)
  788. // Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
  789. // ZMM16-ZMM31 state are enabled by OS)
  790. /// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
  791. if (eax>>5)&7 == 7 && (eax>>1)&3 == 3 {
  792. if ebx&(1<<16) != 0 {
  793. rval |= AVX512F
  794. }
  795. if ebx&(1<<17) != 0 {
  796. rval |= AVX512DQ
  797. }
  798. if ebx&(1<<21) != 0 {
  799. rval |= AVX512IFMA
  800. }
  801. if ebx&(1<<26) != 0 {
  802. rval |= AVX512PF
  803. }
  804. if ebx&(1<<27) != 0 {
  805. rval |= AVX512ER
  806. }
  807. if ebx&(1<<28) != 0 {
  808. rval |= AVX512CD
  809. }
  810. if ebx&(1<<30) != 0 {
  811. rval |= AVX512BW
  812. }
  813. if ebx&(1<<31) != 0 {
  814. rval |= AVX512VL
  815. }
  816. // ecx
  817. if ecx&(1<<1) != 0 {
  818. rval |= AVX512VBMI
  819. }
  820. }
  821. }
  822. }
  823. if maxExtendedFunction() >= 0x80000001 {
  824. _, _, c, d := cpuid(0x80000001)
  825. if (c & (1 << 5)) != 0 {
  826. rval |= LZCNT
  827. rval |= POPCNT
  828. }
  829. if (d & (1 << 31)) != 0 {
  830. rval |= AMD3DNOW
  831. }
  832. if (d & (1 << 30)) != 0 {
  833. rval |= AMD3DNOWEXT
  834. }
  835. if (d & (1 << 23)) != 0 {
  836. rval |= MMX
  837. }
  838. if (d & (1 << 22)) != 0 {
  839. rval |= MMXEXT
  840. }
  841. if (c & (1 << 6)) != 0 {
  842. rval |= SSE4A
  843. }
  844. if d&(1<<20) != 0 {
  845. rval |= NX
  846. }
  847. if d&(1<<27) != 0 {
  848. rval |= RDTSCP
  849. }
  850. /* Allow for selectively disabling SSE2 functions on AMD processors
  851. with SSE2 support but not SSE4a. This includes Athlon64, some
  852. Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
  853. than SSE2 often enough to utilize this special-case flag.
  854. AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
  855. so that SSE2 is used unless explicitly disabled by checking
  856. AV_CPU_FLAG_SSE2SLOW. */
  857. if vendorID() != Intel &&
  858. rval&SSE2 != 0 && (c&0x00000040) == 0 {
  859. rval |= SSE2SLOW
  860. }
  861. /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
  862. * used unless the OS has AVX support. */
  863. if (rval & AVX) != 0 {
  864. if (c & 0x00000800) != 0 {
  865. rval |= XOP
  866. }
  867. if (c & 0x00010000) != 0 {
  868. rval |= FMA4
  869. }
  870. }
  871. if vendorID() == Intel {
  872. family, model := familyModel()
  873. if family == 6 && (model == 9 || model == 13 || model == 14) {
  874. /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
  875. * 6/14 (core1 "yonah") theoretically support sse2, but it's
  876. * usually slower than mmx. */
  877. if (rval & SSE2) != 0 {
  878. rval |= SSE2SLOW
  879. }
  880. if (rval & SSE3) != 0 {
  881. rval |= SSE3SLOW
  882. }
  883. }
  884. /* The Atom processor has SSSE3 support, which is useful in many cases,
  885. * but sometimes the SSSE3 version is slower than the SSE2 equivalent
  886. * on the Atom, but is generally faster on other processors supporting
  887. * SSSE3. This flag allows for selectively disabling certain SSSE3
  888. * functions on the Atom. */
  889. if family == 6 && model == 28 {
  890. rval |= ATOM
  891. }
  892. }
  893. }
  894. return Flags(rval)
  895. }
  896. func valAsString(values ...uint32) []byte {
  897. r := make([]byte, 4*len(values))
  898. for i, v := range values {
  899. dst := r[i*4:]
  900. dst[0] = byte(v & 0xff)
  901. dst[1] = byte((v >> 8) & 0xff)
  902. dst[2] = byte((v >> 16) & 0xff)
  903. dst[3] = byte((v >> 24) & 0xff)
  904. switch {
  905. case dst[0] == 0:
  906. return r[:i*4]
  907. case dst[1] == 0:
  908. return r[:i*4+1]
  909. case dst[2] == 0:
  910. return r[:i*4+2]
  911. case dst[3] == 0:
  912. return r[:i*4+3]
  913. }
  914. }
  915. return r
  916. }